1. Field of the Invention
The present invention relates to an electronic device including a wiring substrate and an electronic part mounted on the wiring substrate.
2. Description of the Related Art
From a standpoint of increase in speed, increase in the number of pins, and decrease in dimension, surface-mounted electronic parts such as a BGA (Ball Grid Array) and a CSP (Chip Scale Package) in which solder bumps are used as connecting terminals are better than packages such as a QFP (Quad Flat Package) in which leads are used. A surface-mounted electronic part includes a rewiring substrate (interposer) and a semiconductor chip. The rewiring substrate includes a first surface and a second surface. The semiconductor chip is mounted on the first surface of the rewiring substrate. A plurality of solder bumps is arranged on the second surface of the rewiring substrate in a matrix form. A wiring substrate has a plurality of lands corresponding to the solder bumps. The solder bumps are respectively coupled with the lands, and thereby the electronic part and the wiring substrate form an electronic device.
When a lead free solder is used, a reflow temperature at a time when the electronic part is mounted on the wiring substrate becomes higher than a case where a solder including lead is used. Thus, the electronic part may bend due to stress caused by a difference in linear expansion coefficients of the electronic part and the wiring substrate. When the electronic part bends, one or more of the solder bumps may collapse and adjacent solder bumps may short out. In the solder bumps arranged in the matrix form, the solder bumps arranged at the outermost periphery, especially, the solder bumps arranged at four corners are liable to collapse and short out.
Also under environment of usage, stress caused by the difference in the linear expansion coefficients of the electronic part and the wiring substrate is applied to connection portions formed by the solder bumps and the lands. In the solder bumps arranged in the matrix form, the solder bumps arranged in the outermost periphery, especially, the solder bumps arranged at four corners are liable to receive large stress. If the electronic device is disposed at a position exposed to a high temperature, such as, an inside of an engine room of a vehicle, the stress increases. Thus, the connection portions formed by the solder bumps and the lands arranged at the four corners are liable to clack. If the adjacent solder bumps are shorting out at a time when the electronic device is disposed in the environment of usage (for example, in the engine room), because the amount of solder at the connection portions decreases by the amount of solder deformed in a horizontal direction, the connection portions that are shorting out are liable to crack. If one connection portion cracks, the stress applied to the connection portions arranged inside the one connection portion increases. Thus, another connection portion arranged inside the one connection portion may also crack. That is, a crack may grow inward.
Therefore, before the electronic device is disposed in the environment of usage, an inspection of connection states of the connection portions of the solder bumps and the lands is required. However, since the electronic part is a surface-mounted type and the solder bumps are arranged in the matrix form, it is difficult to inspect the connections states of all the connection portions of the solder bumps and the lands by external appearance. The connection states can be inspected with an X-ray inspection apparatus, for example. However, because the X-ray inspection apparatus is expensive and it takes a long inspection time, production cost increases.
U.S. Pat. No. 6,225,702 (corresponding to Japanese Unexamined Patent Application Publication No. 11-74407) discloses a semiconductor device in which solder bumps that function as signal electrode terminals are disposed between solder bumps that function as power supply terminals and solder bumps that function as ground terminal, and a short circuit between adjacent bumps is detected by boundary scanning.
Japanese Unexamined Patent Application Publication No. 2001-228191 discloses a method in which some solder bumps arranged at the outermost periphery of a plurality of solder bumps and subjected to the largest mechanical strength due to a difference in thermal expansion coefficients of an electronic part and a wiring substrate are set to solder bumps for confirming connection states, and the connection states of the solder bumps for confirming connection states and corresponding lands of the wiring substrate are detected as a change in impedance.
Japanese Patent No. 4,072,082 discloses a semiconductor device in which solder bumps (pads) arranged at the outermost periphery and the solder bumps arranged inside the outermost periphery are set to solder bumps for power supply, and a resistor and a capacitor are coupled in series between a power source and the ground. In addition, the solder bumps arranged at four corners of the outermost periphery and having a possibility that defect of soldering occur are coupled with an end of the resistor adjacent to the power source, and the solder bumps arranged inside the outermost periphery are coupled with a connection portion of the resistor and the capacitor. Then, a voltage at the connection portion is compared with a reference voltage for determining whether defect of soldering is present.
Japanese Unexamined Patent Application Publication No. 2007-294620 discloses a semiconductor device in which conductive patterns as lands are provided on a rewiring substrate. In the conductive patterns, conductive patterns located at four corners do not provide electric connection between a semiconductor chip and wires of a wiring substrate. In other words, in the solder bumps (conductive balls) arranged in a matrix form, solder bumps located at the four corners are set to nonfunctional bumps that do not provide electric connection between the semiconductor chip and the wires of the wiring substrate. Thus, even if a short circuit or a crack occurs in the solder bumps located the four corners, the semiconductor device can restrict an operation problem.
In the semiconductor device disclosed in U.S. Pat. No. 6,225,702, all the solder bumps provide electric connection between the semiconductor chip and the wires of the wiring substrate. Thus, when a crack occurs at connection portions of the solder bumps and lands located at the outermost periphery, especially, at the four corners due to a stress caused by the difference in the linear expansion coefficients of the electronic part and the wiring substrate in environment of usage, the electronic device, specifically, a circuit in the semiconductor chip may operate abnormally. Therefore, a life of the electronic device may be short.
The semiconductor device disclosed in U.S. Pat. No. 6,225,702 can be modified and the solder bumps can be set to nonfunctional bumps that do not provide electric connection between the semiconductor chip and the wires of the wiring substrate in a manner similar to the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2007-294620. In this case, a short circuit that occurs in the nonfunctional bumps cannot be detected.
In the semiconductor devices disclosed in Japanese Unexamined Patent Application Publication No. 2001-228191 and Japanese Patent No. 4,072,082, a short circuit cannot be detected.